1. Field of the Invention
The present invention relates to a synchronous circuit, particularly to a logic circuit with low EMI (Electro Magnetic Interference) effect by erasing spikes among internal gates.
2. Description of Related Art
The synchronous circuit has been widely used in VLSI or ULSI designs due to fast speed, simple design methodology and ease to be handled by CAD tools. However, a synchronous circuit has some problems in nature, such as clock skew and racing problem, big switching current, big power consumption and spikes among internal logic gates. The occurrence of spikes among internal logic gates is usually caused when two input signals change to opposite logic levels with a small time gap. In most situations, the spike of internal gates will induce EMI effect, which is proportional to       1          T      2        ,
wherein T represents the width of the spikes.
Please refer to FIG. 1, which shows a logic circuit having a first flip-flop stage 11, a group of logic gates 12 and a second flip-flop stage 13. For synchronous purpose, the flip-flops 111, 112 and 113 in the first flip-flop stage 11 and the flip-flops 131 in the second flip-flop stage 13 are designed in the same manner of positive edge triggered. The inputs of the NAND gate 121 are connected to the outputs A and xcx9cB of the flip-flops 111 and 112. The inputs of the NAND gate 122 are connected to the output D of the NAND gate 121 and the output B of the flip-flop 112. The inputs of the NOR gate 123 are connected to the output E of the NAND gate 122 and the output C of the flip-flop 113. Finally, the output F of the NOR gate 123 acts as the input of the flip-flop 131.
FIG. 2 shows a timing diagram of the logic circuit in FIG. 1. It is found that the signal C changes logic level from high to low on the rising edge of the clock signal (denoted as CK in FIG. 2) but the other input E of the NOR gate 123 changes logic level from low to high after a time difference from the rising edge of the clock signal. The difference results in a spike appearing in the signal F, and the spike will induce an EMI effect.
In other words, the prior art circuit will generate spikes among internal gates if their inputs change their logic levels in opposite directions and at different time. In order to solve the above problem, the present invention proposes a novelty spike free circuit with low EMI effect.
The main object of the present invention is to provide a spike free circuit meeting the demand of low EMI effect.
The second object of the present invention is to provide a spike free logic circuit, which can avoid unknown states occurring in a simulation environment.
To obtain the above purposes, the spike free circuit of the present invention comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal. The time shift means shifts input signals, which changes logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring. The group of logic gates is connected to the time shift means. The second flip-flop stage is electrically connected to the group of logic gates and triggered by the first edge of the clock signal. The first edge of the clock signal can be selected from the rising or falling edges of the clock signal. The second edge of the clock signal, as defined above, is the one not being selected.